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AITech International Corp.
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Patent Pending
AIT2139 Video Signal Processor (VSPro)TM
VGA to NTSC/PAL Encoder
The AIT2139 video signal processor converts the non-interlaced analog RGB and syncs (vertical, horizontal or composite) signal from a standard VGA source into a broadcast quality NTSC or PAL video signal. In addition to the S-Video and Composite outputs, the AIT2139 provides optional interlaced analog RGB or analog Y/PrPb output formats. Advanced digital signal processing and Flic-FreeTM digital filter technology provide a clean and stable video display. The AIT2139 is a master-mode-only video signal processor. Scan rate conversion is accomplished through an external SDRAM or EDO memory which allows the AIT2139 to accept VGA input not necessarily synchronized with TV timing. The AIT2139 accepts multi-sync inputs, supporting resolutions from 640x480 (up to 85 Hz refresh rate) to 1024x768 (60 Hz). A proprietary digital scaler fits the computer image, with borders and menu bars visible for all of the above resolutions, into an underscaned TV-Size image for both NTSC and PAL video standards. The AIT2139 also provides Zoom, Freeze, Pan, and Scroll capabilities. The AIT2139 can be controlled from pins or via I2C. All video processing is done in the digital domain with no tuning circuits. Oversampling techniques in the digital encoder result in very simple and inexpensive analog output filters. The output DACs generate standard video-level signals into a 50 load (150 termination at the source and 75 load at the video monitor). The AIT2139 requires an absolute minimum of external components. Precision timing is derived from a 27 MHz crystal or clock reference. The AIT2139 conserves power by supporting the VESA DPMS, as well as a complete chip power-down mode. The AIT2139 is fabricated in a sub-micron CMOS process and packaged in 128-lead MQFP. Performance is guaranteed from 0C to 70C (TA).
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Supports MacrovisionTM 7.X anti-copy protection Single-chip, crystal-controlled, all-digital Video Signal Processing Simultaneous display on Monitor, LCD and TV Multiple frequency input formats: 640x480, up to 85 Hz 800x600, up to 85 Hz 1024x768, up to 60 Hz Underscan, Freeze, Zoom, Pan and Scroll Supports NTSC, NTSC-EIAJ, and PAL B/D/G/H/I/M/N standards Supports Macintosh, NEC-PC98 and PC Line-21 and Line-284 Closed Captioning Support 3-Channel 8-Bit ADC inputs for true 16.7 million color conversion 3-Channel 10-bit DAC outputs Proprietary memory compression reduces external memory size External EDO (256K X 16-Bit) memory interface External SDRAM (1M X 16-Bit) memory interface Fully programmable through I2C port or hardware (pin-based) controls Flic-FreeTM filter Selectable TV output format - Composite, S-Video, Y/PrPb or RGB/SCART Auto detect input video mode Auto detect the presence of the TV Single +5V power supply
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Computer Compatible TV Internet Appliances / TV / Set-top Box Advanced VGA to Video Scan Converter DVD movie playback
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AIT2139 Block Diagram
XTAL1/27MHz
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External SDRAM/EDO Memory Module
PDO (Adr) PDI (Data I/O)
HSOUT
VSOUT
XTAL2
Control
16
16
VGAHS / VGACS VGAVS
Timing Generation
Memory Management Unit
Memory Configuration
7
COMPOSITE SYNC 2 OUTPUT_FORMAT_SELECT
R
8-bit ADC
R
Y
10-bit DAC
G / Y / COMPOSITE
Filter
V
B
8-bit ADC
B
10-bit DAC
B / U / LUMA
Control and Setup
Toggle Control I2 C Register Control Block Level Control Set-Up Power Saving
Color Bar Test Pattern LUT
Sub-Carrier Waveform Generator LUT
TVSTD0 TVSTD1
PAL_NTSC
POS L
I2 C_ADR
I2 C_SDA
BLANK
POS D
POS U
POS R
I2 C_SCL
VRT
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The AIT2139 comprises all of the circuitry necessary to convert analog RGB signals from a graphic controller or RAMDAC into standard base band video signal adhering to worldwide NTSC and PAL standards. The AIT2139 is a stand-alone VGA-to-TV video processor with user selectable RGB, Y/PrPb, S-Video or Composite output. The AIT2139 is a master mode only video converter. Using external SDRAM or EDO memory, the input timing and output video timing become independent. The AIT2139 has the capability to accept VGA input not necessarily synchronized with TV timing, to manipulate the image and to generate extremely accurate video output signals. The internal line cache provides anti-flicker conversion. The AIT2139 provides additional image control such as Zoom by 2, positioning and panning. A built-in digital scaler scales down the computer image vertically and horizontally to generate an underscan TV-size display image.
FREEZE
The AIT2139 operates entirely in the digital domain between A/D conversion of graphic input signals and D/A conversion of Composite, S-Video, RGB or YUV output signals. Operation The analog VGA signal is digitized by three 8-bit A/D converters operating up to 48 MHz. The standard signal range is from 0 to 0.85V, but other values can be accommodated by varying the reference voltage. Clocks for the input portion of the AIT2139 are generated by an internal phase-locked loop with an integral divide-by-N counter. This clock generator uses the VGA horizontal sync or composite sync as its input reference frequency. The clock generated by the PLL and counter is locked to the incoming line rate and is used to digitize a fixed number of pixels per line. With the external SDRAM or EDO memory, the sampled data is stored and retrieved by the video signal processor. The clock for the processor portion of the AIT2139 is crystal-controlled at 27 MHz. It is generated by connecting a standard 27 MHz oscillator or crystal to an internal oscillator circuit. As a result of de-coupling the input and output, the stable time-base ensures adherence to the television standards.
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FILTER
ZOOM
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S-VIDEO
G
8-bit ADC
G
Color Space Converter
U
Flic-Free
(T M )
TV-Size Underscan Scaler
Digital NTSC / PAL Video Encoder with Macrovision 7.xx
10-bit DAC
R / V / CHROMA
VGA to NTSC/PAL Encoder
Input A/D conversion Eight-bit A/D converters are used on each of the red, green, and blue input video signals at up to 48MHz sampling rate. HSYNC and VSYNC are buffered by Schmitt trigger gates. Typical RGB signal range is from 0 to 0.85V. A different reference voltage can be applied to VRT in order to override the internal reference to accommodate different input signal ranges. This externally supplied reference voltage should be higher or equal to the maximum RGB signal range. Converting from RGB to Components Digital video processing within the AIT2139 is done with common YUV color components. The output of the RGB-to-YUV matrix operates in 24bit with the YUV data decimated to 4:2:2 format. Flicker Filtering A finite impulse response digital filter is used to reduce flicker due to single line elements of the graphic input image and the interlaced structure of NTSC and PAL video. This is constructed using proprietary AITech algorithms. Scan Conversion Operation Video scan-rate and timing are generated by the control logic based on the input VGA-compatible graphic signal. The AIT2139 front end comprises all the circuitry in the signal path from the A/D converters to the vertical filter network. All front-end circuits operate at the phase-locked clock frequency. This means that digital video pixels (16-bits of YUV 4:2:2) are written into the external FIFO or SDRAM or EDO memory at the same rate as the pixel clock frequency. Master Mode In master-mode operation, the processor internally generates all the timing and sync signals, and provides the Horizontal Sync, Vertical Sync, and an internal Pixel Data Clock to the external memory devices. The processor is capable of accepting the multi-sync inputs in the master mode operation. The processor provides a clock and an odd/even signal to the FIFO or the external memory devices. The VGA data read-in time is not necessary to be synchronized with the write-out time to the processor. Depending on the memory configuration, the AIT2139 supports VGA 640 x 480, SVGA 800 x 600, XGA 1024 x
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768, Mac 640 x 480, 832 x 624, and NEC 640 x 400 underscan modes. Positioning Four positioning function pins allow the encoded graphic image to be shifted up/down and left/right in case the video image needs to be centered or repositioned. Zooming and Panning The Zoom feature doubles the video image size in both the horizontal and vertical directions. Each VGA pixel will become an equivalent of 4-pixels displaying to video. In the Zoom mode, the positioning function pins will act as panning control to pan the zoomwindow across the expanded VGA image. Internal Digital Video Encoder The processor section of the AIT2139 accepts the digital video data at the external memory device I/O port in YUV 4:2:2 format. The processor input is separated into the luminance and chrominance components. The chrominance signals are modulated by a digitally synthesized subcarrier. The luminance and chrominance signals are separately interpolated to twice the pixel rate, and converted into analog SVideo signals by two 10-bit D/A converters. The analog Composite video signal is output by a third 10bit D/A converter. The AIT2139 also provides pinselectable analog Y/PrPb(Sync on Y) or RGB output format for applications that demand the highest quality display. A Color Space Converter is used to convert Y/PrPb to RGB format. Encoder Timing The processor operates from a single clock at 27 MHz. Different preset timing parameters are selected with the format control pins. These pins configure the AIT2139 for NTSC, NTSC-EIAJ, and PALB/D/G/H/I/M/N television standards. Blanking The AIT2139 is designed to blank the video screen to blue by setting BLANK control input to High. Power Conservation The AIT2139 supports the VESA DPMS power down mode to conserve power. The operational state of the AIT2139 is controlled by the pulse activity on VGA HSync and VSync according to Table 3. I2C can also be used to detect the present of HSync and Vsync. When the AIT2139 is not in use, it can further conserve power by using the PWRDN pin or via I2C.
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Type/Value
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL VRT +0.85V +0.85V +0.85V TTL TTL 1 V p-p 1 V p-p 1 V p-p TTL TTL TTL +1.235V 140 TTL
Signal Type Clock Global Controls
Name
XTAL1-2 TVSTD1-0 PAL_NTSC FIL RESET\ PHASE YUV_OUT RGB_OUT FREEZE ZOOM OVRSCN POSU, L, R, D
Function
Subcarrier Reference Crystal/Clock Video Output Standard Select Flicker Filter Select Reset Sampling Phase Control YUV output Select RGB output Select Video Image Freeze Select Video Image Zoom Select Overscan and Underscan Select Video Image Position Controls Composite Video D/A Control S-Video D/A Control Blank Screen Generator Encoder Reset Analog RGB Inputs A/D Converter Reference Input, Buffered A/D Converter Reference Output, Buffered A/D Converter Reference Input, Unbuffered VGA Horizontal Sync VGA Vertical Sync NTSC/PAL Video Output Luminance-only Video Chrominance-only Video Buffered VGAHS Output Buffered VGAVS Output Composite Synchronization Signal Output D/A Voltage Reference Input/Output Current-setting Resistor Bi-directional Data I/O from/to memory
Package/Pin MQFP
61, 62 90, 98 103 104 3 120 106 107 123 102 105 113, 112, 111, 110 67 66 122 86 83, 88, 94 80 81 93 125 127 75 72 77 126 128 82 74 70 37, 38, 39, 40, 41, 43, 44, 45, 46, 47, 48, 49, 50, 51, 53, 54 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28,30 31 32 33
Encoder Controls
Video Inputs
CVIDEN SVIDEN BLANK EN_RST\ R, G, B VTIN VTOUT VRT HSRAW VSRAW
Video Outputs
COMPOSITE LUMA CHROMA HSOUT VSOUT CSYNC
Encoder Reference SDRAM Memory I/O
VREF RREF PDI0~15
PDO0~11
Address Output Pins from memory
TTL
PDO_12 PDO_13 PDO_14
CAS\, Column Address Strobe RAS\, Row Address Strobe DQM, Data Input/Output mask
TTL TTL TTL
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PDO_15 MW_CLK MW_RST MW_EN SDR MWR\, Memory Read/Write Input CLK, Clock Signal CKE, Enable/Disable Clock Signal CS\, Enable/Disable Command Decoder SDRAM Memory Select Bi-directional Data I/O from/to memory TTL TTL TTL TTL TTL TTL
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34 14 15 16 121 37, 38, 39, 40, 41, 43, 44, 45, 46, 47, 48, 49, 50, 51, 53, 54 17, 18, 20, 21, 22, 23, 24, 25, 26 31 32 33 34 118 116 117 13, 36, 58* 1, 6, 9, 59, 71, 92, 101, 115, 100,109 96, 91, 85, 78, 79, 65 12 10 2, 7, 19, 29, 42, 52, 63, 87, 97, 114, 119, 124 64, 76, 84, 89, 95, 108 4, 8, 35, 60, 68, 99, 55, 56, 57 5 11 69 73
EDO Memory I/O
PDI0~15
PDO0~8 PDO_12 PDO_13 PDO_14 PDO_15
2
2
Address Output Pins from memory CAS\, Column Address Strobe RAS\, Row Address Strobe MOE\, Memory Output Enable MWR\, Memory Read/Write Input I C Serial Data Input (logic "high" or logic "low") I C Serial Data Input (<400KHz) Slave Device Address Select SDRAM I/O Power Supply Digital Power Supply Analog Power Supply A/D Phase Locked Loop Power A/D Phase Locked Loop Ground Digital Ground
2 2
TTL TTL TTL TTL TTL TTL Tri-Stat TTL TTL +3.3V +5.0 V +5.0 V +5.0 V 0.0 V 0.0 V
I C-bus
I C_SDA I C_SCL I C_ADR VDD_3.3
2 2
Power
VDD VDDA VDDPLL
Ground
GNDPLL DGND
AGND
Analog Ground Do Not Connect Testing ONLY. Must Tie to Low PLL Low Pass Filter Compensation Capacitor Power down enable
0.0 V TTL Analog Analog TTL
No Connect MISC
NC T_EN PLL_LPF C_COMP
PWRDN
PD_EN
Note: * PIN13, 36, 58 also can be connected to VDD
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A/D Converter Interface R, G, B Red, Green, Blue analog input from graphic card/computer. The expected voltage range of these input signals is from 0.0 to 0.85 Volts. HSRAW Horizontal sync input from Graphic controller. The polarity of graphic HS is internally corrected to active Low whether the incoming graphic HS is active High or active Low. Vertical sync input from Graphic controller. The polarity of graphic VS is internally corrected to active Low whether the incoming graphic VS is active High or active Low. A/D reference in, unbuffered. This pin should be connected to a voltage follower or VTOUT pin. Input to top reference voltage buffer. External 0.1 uF bypass capacitor should be used. Top reference voltage buffer output that may be connected to VRT to supply current to A/D converter reference resistors. In power down mode, VTOUT drops to zero.
VSRAW
VRT VTIN VTOUT
Clock Generators XTAL1-2 Connection points for the 27 MHz oscillator or crystal. If an oscillator is used, its output should be fed into XTAL1. If a crystal is used, it should be connected across XTAL1 and XTAL2 along with the proper resistors and/or capacitors, as required by the crystal manufacturer. Use only a fundamental type crystal. AIT2139 Controls TVSTD1-0 Video output standard select. The AIT2139 has preprogrammed timings, sub-carrier frequencies PAL_NTSC and phase data that corresponds to worldwide NTSC and PAL standards. These input select pins direct the appropriate timing and sub-carrier data to the processor for set-up (refer to Table 1). FIL Vertical Filter Mode selects (state machine). The 3-line flicker reduction filter may be configured for 3-line filtering, 2-line filtering, and no vertical filtering modes with these pins. Pulsing the FIL control pin will cycle through the different filtering modes as shown in Table 2. When High, the AIT2139 is configured for YUV output, the COMPOSITE, LUMA, and CHROMA output pins will output Y, U, and V respectively. When Low, YUV output is disabled. When High, the AIT2139 is configured for RGB output, the CHROMA, COMPOSITE, and LUMA output pins will output R, G, and B respectively. When Low, RGB output is disabled. When brought to High, writing to the external field store devices stops on the next falling edge of VSYNC\. When brought to Low, writing to the external field store devices resumes on the next falling edge of VSYNC\. A pulse triggering pin, i.e., a pulse toggles the state of zoom in /out. The video image size can be doubled in both the horizontal and vertical directions (note: this makes the image 4x larger) during zoom in. The video image displays can be set back to the normal size by toggling this pin.
YUV_OUT
RGB_OUT
FREEZE
ZOOM
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POSD, POSR, POSU, POSL
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The position controls change the processor timing relative to incoming video so that the viewed image may be shifted right or down, to reveal portions of the image that may be found near the edges or in the overscan areas. Vertical position is adjusted 2 lines per frame, total of 128 lines. Horizontal position is moved 2 pixels per frame, total 128 pixels. Only POSD, POSR are used during 2_POS = 1 (High). When in the two-toggle positioning mode, upon reaching the end, the video image will revert to the most upper left position. In the 4-toggle positioning mode (2_POS = 0 or Low), reversion is not supported and all 4 positioning controls have to be used in order to scroll back the image. During Zoom operation, the 4 positioning controls remains available, and are used for panning the image across the active video area. All four positioning control pins are level sensitive pins. POSD and POSR are active Low. POSU and POSL are active High. A toggle input. Internally pulled-low (equal to logic "0" or Low). The video output is toggled between underscan and overscan. OVRSCN is only available at 640 X 480 resolution.
OVRSCN
Table 1. TV Standard Control Television Standard NTSC NTSC - EIA PAL - M PAL - N PAL - BDGHI PAL - Combination N PAL_NTSC 0 0 0 1 1 1 TVSTD0 0 1 0 0 1 1 TVSTD1 0 0 1 0 0 1
Table 2. FIL Filter Mode Select Sequence FIL Filter Mode 3-line 2-line No filter Color bars
Encoder Controls CVIDEN Composite video D/A control. When High, the Composite D/A converter is always enabled. When Low, the Composite D/A converter is disabled when TV is not connected to the Composite port, vice versa. The Composite D/A status can be readback from the Output Control Register, OCR[4], through I2C. SVIDEN S-Video D/A control. When High, the CHROMA and LUMA D/A converters are always enabled. When Low, the CHROMA and LUMA D/A converters are disabled when TV is not connected to the S-Video port, vice versa. The CHROMA and LUMA D/A status can be readback from the Output Control Register, OCR[3] and OCR[5] respectively, through I2C. When High, BLUE screen is displayed on the screen until BLANK goes Low. When Low, the all timing for the encoder will be reset. This is applicable when sync with an external video source.
BLANK EN_RSTN
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Encoder Interface VREF The voltage reference pin is the output of an internal 1.2 Volt band-gap type voltage reference. If this pin is left unconnected (except for a 0.1 microfarad capacitor to ground for noise de-coupling) the internal reference will be used for the three D/A converters. If an externally generated voltage reference of +1.2 Volts is applied to the VREF pin, it will override the internal voltage reference and become the new reference for the D/A converters. RREF A resistor of 140 Ohms is connected between the RREF terminal and ground to set up the reference current for the three internal D/A converters. The value of this resistor determines the full-scale output current (and therefore the peak video level) of the D/A converters. This analog base band composite video output can drive a 1 VPP video into a 50 (150//75) terminated line. The composite signal contains all the sync, sub-carrier and active video information to drive monitors, projectors, VCRs or other video input devices. This pin will output the Y(with sync)/G component of YUV/RGB, when YUV_OUT/RGB_OUT pin is pulled High. This analog base band monochrome video output can drive a 1 VPP video into a 50 (150//75) terminated line. The luminance signal contains all sync and active video information necessary to drive black-and-white video input devices. This pin will output the U/B component of YUV/RGB, when YUV_OUT/RGB_OUT pin is pulled High. This analog chrominance video output drives a 50 Ohm terminated line. The CHROMA signal, when combined with the LUMA output signal comprises an S-Video two-wire video signal and is suitable for driving monitors, projectors, VCRs and other S-Video input devices. This pin will output the V/R component of YUV/RGB, when YUV_OUT/RGB_OUT pin is pulled High. Composite synchronization signal output for the converted video signal. In general, this pin is left not connected except for GENLOCK or other purposes.
COMPOSITE
LUMA
CHROMA
CSYNC
SDRAM Memory I/O PDI0-15 Pixel Data Input/Output pins for YUV digital component video to/from the external line store devices. PDO0-10 PDO_12 PDO_13 PDO_14 PDO_15 MW_CLK MW_RST MW_EN SDR Memory address output pin. CAS\, Column Address Strobe. RAS\, Row Address Strobe. DQM, Data Input/Output Mask. MWR\, Memory Read/Write Enable. CLK, Clock Signal. CKE, Enable/Disable Clock Signal. CS\, Enable/Disable Command Decorder. SDRAM memory select pin. When High SDRAM memory configuration is selected. This pin is not connected when EDO memory is used instead of SDRAM.
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EDO Memory I/O PDI0-15 Pixel Data Input/Output pins for YUV digital component video to/from the external line store devices. PDO0-8 PDO_12 PDO_13 PDO_14 PDO_15 Memory address output pin. CAS\, Column Address Strobe. RAS\, Row Address Strobe. MOE\, Memory Output Enable. MWR\, Memory Read/Write Enable.
Power and Ground VDD +5 Volt power to the internal digital circuits. VDDA VDDPLL +5 Volt power to the internal analog circuits. VDD and VDDA must come from the same source. +5 Volt power to the internal A/D phase locked loop. It should originate from the same power plane but not to share the same via with any other power supplies. Ground point for the internal A/D phase locked loop. It should originate from the same ground plane but not to share the same via with other ground points. Ground point for the internal digital circuits. Ground point for the internal analog circuits. DGND and AGND should be connected to the same ground plane.
GNDPLL
DGND AGND
DPMS VESA DPMS power-down mode is controlled by the pulse activity on HSRAW and VSRAW according to the following table: Table 3. DPMS Power Down Select DPMS State On Stand-by Suspend Off VGAHS active inactive active inactive VGAVS active active inactive inactive AIT2139 state On, video active Stand-by, blue screen displayed Suspend, blue screen displayed Off, AIT2139 powered-down
The VGAHS and VGAVS signal can be readback from the Output Control Register (OCR[1:0]) through I2C. This function will allow other devices in the application to support the standard VESA DPMS so as to conserve more power.
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The AIT2139 provides an I2C interface capability, which simplifies both the design and operation of the product. The AIT2139 I2C bus uses two bi-directional wires, serial data (SDA) and serial clock (SCL) to transfer information between devices connected to the bus. Each device is recognized by a unique address. The AIT2139 I2C interface is only for slave mode so that the clock for synchronizing data transfer is generated by an I2C master. There are ten accessible I2C control registers. Writing to this control registers will override all other hardware or software control. Asserting chip reset causes the AIT2139 to regain set-up controls via hardware or software. I2C Interface Characteristics 1. Serial data and clock rate up to 100K Hz. 2. Always in slave mode. 3. All registers can be read/write. 4. Each access must include an 8-bit sub-address. 5. No response to general calls. I2C Input Pin The AIT2139 I2C interface is controlled by three hardware pins. * I2C_SDA : I2C serial data input pin. * I2C_CLK : I2C serial clock input pin. * I2C_ADR : This pin select one of the slave device addresses. I2C Device Address The I2C interface responds to the slave device address selected by the I2C_ADR pin. I2C_ADR 0 1 Slave Device Address 10001000 (88h) 10001010 (8Ah)
I2C Sub-Address The I2C Interface writes to one of the ten control registers. These control registers control various functions of the chip. The control register data will override current hardware or software settings. Each I2C access must include one of these sub-addresses as defined in the following. The user must use the correct sub-address; otherwise the AIT2139 might lock into the wrong operating state.
SubAddress 0 1 2 3 4 5 7 8 9 A B C D E
Mode R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Register Definition Status register LSBs of 11-bit P1 term MSBs of 16-bit P2 term LSBs of 16-bit P2 term MSBs of 16-bit P3 term LSBs of 16-bit P3 term Vertical Position Register Encoder Control register Input Control Register MSBs of 11-bit P1term & MSBs of 11-bit subcarrier phase adjust PLL control register LSBs of PLL modulus Input Mode Detect Register Aperture correction register
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11 16 1D 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 38 39 3A 3B 3D 3E 3F R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W Output Control Register Horizontal Position Register LSBs of sub-carrier phase adjustment MacrovisionTM CPS0 byte MacrovisionTM CPS1 and CPS2 MacrovisionTM CPS3 and CPS4 MacrovisionTM CPS5 and CPS6 MacrovisionTM CPS7 and CPS8 MacrovisionTM CPS9 and CPS10 MacrovisionTM CPS11 and CPS12 MacrovisionTM CPS13 and CPS14 MacrovisionTM CPS15 and CPS16 MacrovisionTM CPS17 and CPS18 MacrovisionTM CPS19 and CPS20 MacrovisionTM CPS21 and CPS22 MacrovisionTM CPS23 and CPS24 MacrovisionTM CPS25 and CPS26 MacrovisionTM CPS27 and CPS28 MacrovisionTM CPS29 and CPS30 MacrovisionTM CPS31 and CPS32 Close Caption first byte odd field Close Caption second byte odd field Close Caption first byte even field Close Caption second byte even field Device ID register MacrovisionTM control byte MacrovisionTM control byte verify register
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I2C Write Cycle Format The AIT2139 I2C interface supports read and write cycle operations by the master device. I2C WRITE and READ access has the following transfer protocol (continuous write mode is also supported): [Write] Start Write
Device Addr Write
Ack
Sub Addr Start
Ack
Data (N)
Ack (N)
Stop
[Read] Start Device Addr Start: Slave Address:
Ack
Sub Addr
Ack
Device Addr
Read
Ack
Data
Ack
Stop
The start condition is defined as the falling edge of the SDA signal while SCL (serial clock) is high. The 7-bit slave device address used by the AIT2139. Once communication is established, the AIT2139 expects a device address ID from the master device. This device address is determined by the state of the I2C_ADR pin. This bit is "0" for I2C write operation and "1" for I2C read operation. This bit is the acknowledge bit. The AIT2139 pulls the SDA data line to logic "low" to acknowledge successful reception of the 8-bit data.
Write: Ack:
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Sub Address: Data: Stop: The 8-bit sub-address for accessing to one of the control registers. The 8-bit value to be written into the control register.
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The stop condition is initiated to terminate the I2C communication. It is defined as the rising edge of SDA signal while SCL is logic "high".
H L
SDA
SCL L Start Condition
H
1-7 8 9 1-8 9 1-8 9
Device Address
Write
AIT 2138 Acknowledge
Data 1
AIT 2138 Acknowledge
Data N+1
AIT 2138 Acknowledge
Stop Condition
Figure 1. An I2C interface transfer protocol of the AIT2139 for WRITE operation.
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SDA L SCL L
Start Condition Device Address Write
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H L
H
H
1-7 8 9 1-8 9
H
1-7 8 9 1-8 9
L
AIT AIT Start Data 1 2138 2138 Condition Acknowledge Acknowledge Device Addr es s Read AIT AIT 2138 Data N+1 2138 Acknowledge Acknowledge Stop Condition
Figure 2. An I2C interface transfer protocol of the AIT2139 for READ operation. Once the I2C interface updates a control register. The contents of the control register will override other external hardware or software controls. Once written, the I2C control information can only be changed by writing new information via the I2C port or by asserting the reset pin of the AIT2139. Access to each control register must start with the START condition and end with the STOP condition.
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Status Register (SR) Bit Type Bit 7 Bit 6 Bit 5:2 Bit 1 7 Reserve 6 Reserve 5 R 4 R 3 R 2 R Address : 00H Bits : 8 1 0 R R
Bit 0
RESERVED RESERVED VGA INPUT MODE LINE 21 CAPTION 1 = Bytes not sent 0 = Bytes had been sent LINE 284 CAPTION 1 = Bytes not sent 0 = Bytes had been sent
P1 LSB Register (P1) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 01H Bits: 8 1 0 R/W R/W
Bit 7:0 P1 TERM LSB P1[7:0] The P1 term is an 11-bit number. The least significant 8-bit is in this register. The most significant 3-bit is located at sub-address A. The P1, P2, and P3 terms control the color sub-carrier frequency.
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P2 MSB Register (P2) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
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Address: 02H Bits: 8 1 0 R/W R/W
Bit 7:0 P2 TERM MSB P2[15:8] The P2 term is a 16-bit number. The most significant 8-bit is in this register. The least significant 8-bit is located at sub-address 3. The P1, P2, and P3 terms control the color sub-carrier frequency.
P2 LSB Register (P2) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 03H Bits: 8 1 0 R/W R/W
Bit 7:0 P2 TERM LSB P2[7:0] The P2 term is a 16-bit number. The least significant 8-bit is in this register. The most significant 8-bit is located at sub-address 2. The P1, P2, and P3 terms control the color sub-carrier frequency.
P3 MSB Register (P3) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 04H Bits: 8 1 0 R/W R/W
Bit 7:0 P3 TERM MSB P3[15:8] The P3 term is a 16-bit number. The most significant 8-bit is in this register. The least significant 8-bit is located at sub-address 5. The P1, P2, and P3 terms control the color sub-carrier frequency.
P3 LSB Register (P3) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 05H Bits: 8 1 0 R/W R/W
Bit 7:0 P3 TERM LSB P3[7:0] The P3 term is a 16-bit number. The least significant 8-bit is in this register. The most significant 8-bit is located at sub-address 4. The P1, P2, and P3 terms control the color sub-carrier frequency.
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Vertical Position Register (VPR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
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Address: 07H Bits: 8 1 0 R/W R/W
Bit 7:0 VERTICAL POSITION The 8-bit binary value defines the vertical position of the output video image. The 8-bit value is a 2-compliments signed number. Each input mode has its own startup default value. Subtracting from the start up default value will move the screen downward. Adding to the start up default value will move the screen upward. Each step represents 1 pixel. Since VPR is a signed-value, the most significant bit of this register is the sign bit. Note that writing into this control register will override the current setting. The vertical position hardware pins are disabled until the chip is being reset.
Encoder Control Register (ECR) Bit Type Bit 7 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 08H Bits: 8 1 0 R/W R/W
COLOR BAR ENABLE 1 = Enable color bar output 0 = Normal output Bit 6 BLANK 1 = Blank output 0 = Normal output Bit 5,2,4 TV OUT FORMAT 000 = NTSC (7.5 IRE setup) 001 = NTSC (no setup) (NTSC-EIA) 010 = PAL-N 011 = PAL I,G,H,B,D 100 = PAL-M 101 = NTSC (no setup) (NTSC-EIA) 110 = PAL I,G,H,B,D 111 = PAL combination N Bit 3 UV_SEL 0 = Swap U, V color processing 1 = Normal color processing Bit 1 NO_ROMS Must be zero Bit 0 NO_V_DT Must be zero This register controls the encoder function. For PAL TV out format, the input process control register IPCR[4] must be set to 1.
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Input Process Control Register (IPCR) Bit Type Bit 7 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
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Address: 09H Bits: 8 1 0 R/W R/W
ZOOM 1 = Enable Zoom output 0 = Normal output Bit 6 OVERSCAN 1 = Enable Overscan output (only at 640x480) 0 = Normal output Bit 5 FREEZE 1 = Freeze output 0= normal output Bit 4 PAL SELECT 1 = PAL output 0 = NTSC output Bit 3:2 FILTER TYPE 00 = 3 lines filter 01 = 2 lines filter 10 = No flicker filter Bit 1:0 HORIZONTAL FILTER 2 = high bandwidth low pass filter 1 = low bandwidth low pass filter 0 = no horizontal low pass filter Sub-Carrier Misc Register (SCMR) Bit Type Bit 7 7 R/W 6 R/W 5 R/W 4 R/W 3 Reserved 2 R/W Address: 0AH Bits: 8 1 0 R/W R/W
RESET SUB-CARRIER PHASE 1 = Reset phase every 8 frames 0 = No reset Bit 6:4 MSB OF SUB-CARRIER PHASE SCPR[10:8] Bit 3 Reserved Bit 2:0 MSB OF P1 TERM P1[10:8]
PLL Control Register (PCR) Bit Type Bit 7:6 Bit 5:4 Bit 3 Bit 2 Bit 1 Bit 0 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 0BH Bits: 8 1 0 R/W R/W
MSB OF PLL MODULUS PMR[9:8] INTERNAL CLOCK DELAY ADJUST PLL PRE_D2 CONTROL PLL OUT_D2 CONTROL PLL FEB1_D2 CONTROL RESET
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PLL Modulus Register (PMR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
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Address: 0CH Bits: 8 1 0 R/W R/W
Bit 7:0 LSB OF PLL MODULUS PMR[7:0]
Input Mode Detect Register (IMDR) Bit Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 0DH Bits: 8 1 0 R/W Reserved
V FREQ 1 = within range of V Freq > 63 Hz V LINE COUNT 1 = More than 470 vertical lines V LINE COUNT 1 = More than 530 vertical lines V LINE COUNT 1 = More than 700 vertical lines V FREQ 1 = within range of 63 Hz < V freq < 69 Hz V FREQ 1 = within range of 69 Hz < V freq < 73 Hz V FREQ 1 = within range of 73 Hz < V freq < 79 Hz RESERVED
Aperture Control Register (ACR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 0EH Bits: 8 1 0 R/W R/W
Bit 7 LINE 21 CLOSE CAPTION ENABLE Bit 6 LINE 284 CLOSE CAPTION ENABLE Bit 5:4 Y-CHANNEL DELAY 00 = No delay 01 = 1clock delay 10 = 1 clock delay 11 = 2 clock delay Bit 3 MAXIMUM CORRECTION Bit 2 CORRECTION/2 Bit 1 CORRECTION/4 Bit 0 CORRECTION/8
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Output Control Register (OCR) Bit Type Bit 7 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
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Address: 11H Bits: 8 1 0 R R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POWER DOWN 1 = Enable power down 0 = normal operation POWER DOWN CLOCK 1= Enable power down clock generator 0 = normal operation DISABLE Y DAC 1 = Disable Y DAC 0 = Enable Y DAC DISABLE COMPOSITE DAC 1 = Disable composite DAC 0 = Enable composite DAC DISABLE C DAC 1 = Disable C DAC 0 = Enable C DAC CHROMA LOW PASS FILTER BANDWIDTH CONTROL 1 = High 0 = Low HSYNC 1 = Present 0 = Absent VSYNC 1 = Present 0 = Absent
The OCR bit-3, 4 and 5 is used to enable/disable the Y, Composite and C DAC respectively. On readback, it can be used to detect the present of TV connection to the S-Video or Composite port (CVIDEN and SVIDEN pins must be tied to Low).
Horizontal Position Register (HPR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 16H Bits: 8 1 0 R/W R/W
Bit 7:0 HORIZONTAL POSITION The 8-bit binary value defines the horizontal position of the output video image. The 8-bit value is a 2compliments number. Each operating mode has its own startup default value. Subtracting from the start up default value will move the screen to the right. Adding to the start up default value will move the screen to the left. Each step represents 2-pixels. Since HPR is a signed-value, the most significant bit of this register is the sign bit. Note that writing into this control register will override the current setting. The horizontal position hardware pin is disabled until the chip is being reset.
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Sub-Carrier Phase Register (SCPR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
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Address: 1DH Bits: 8 1 0 R/W R/W
Bit 7:0 LSB OF THE 11-BIT SUB-CARRIER PHASE REGISTER SCPR[7:0] The most significant bits of the sub-carrier phase register is located at sub-address A. This adjustment is a 11-bit number with the range of 0 through 2048 representing 0 through 360 degree of phase adjustment.
MacrovisionTM Control Registers (MVCR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 20H~30H Bits: 8 1 0 R/W R/W
Refer to the I2C registers summary for the definition of these registers. For detail description of these registers, please refer to the MacrovisionTM 7.01 specification.
Close Caption Data Register (CCDR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 38H~3BH Bits: 8 1 0 R/W R/W
Sub-address 38h and 39h contain the first byte and second byte of the Line 21 Caption respectively. Odd parity for each byte is automatically generated during transmission. Before writing to these two registers, the users should check the Line 21 Caption flag in sub-address 0 (SR) bit 1 is clear. This flag is set automatically when the subaddress 38h is written. Writing into the sub-address 39h will not set this flag. Sub-address 3Ah, 3Bh contain the first byte and second byte of the Line 284 Caption respectively. Odd parity for each byte is automatically generated during transmission. . Before writing to these two registers, the users should check the Line 284 Caption flag in sub-address 0 (SR) bit 0 is clear. This flag is set automatically when sub-address 38h is written. Writing into subaddress 3Bh will not set this flag.
Device ID Register (IDR) 7 Bit R Type
6 R
5 R
4 R
3 R
2 R
Address: 3DHBits: 8 1 0 R R
This register contains the device ID number. The value for this revision is 11 hex.
MacrovisionTM Control Register (MVCR2) Bit Type Bit 7 Bit 6 Bit 5 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 3EH Bits: 8 1 0 R/W R/W
AGC ENABLE RESERVED PSUEDO-SYNC ENABLE
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Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BACK PORCH AGC ENABLE COLOR STRIPS ENABLE RESERVED REDUCE HORIZONTAL SYNC REDUCE VERTICAL SYNC
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The MVVR[5:0] registers must be set to 3E hex before accessing this register(MVCR2).
MacrovisionTM Verification Register (MVVR) Bit Type 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W
Address: 3FH Bits: 8 1 0 R/W R/W
Bit 7 RESERVED Bit 6 RESERVED Bit 5:0 MACROVISIONTM ACCESS MVID[5:0] The MVID term is a 6-bit value that must be set to 3E hex before accessing the MacrovisionTM Control Registers (MVCR2), writing any other value will lock the MacrovisionTM Control Registers (MVCR2).
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The AIT2139 supports closed captioning conforming to the standard Television Synchronizing Waveform for Color Transmission in Subpart E, Part 73 of the FCC Rules and Regulations and EIA-608. Closed captioning and text are transmitted during the blanked active line-time portion of Line 21. The AIT2139 also supports the extended data services (EDS or XDS), which is transmitted during the blanked active line-time portion of Line 284. XDS is responsible for program name, start time, end time, call sign, etc. Closed captioning consist of a 7-cycle sinusoidal burst that is frequency-locked and phase-locked to the caption data. After which the blanking level is maintained for two data bits, followed by a "1" start bit. The start bit is followed by 2 bytes of 16 bit data comprised of two 7 bit & 1 odd parity ASCII characters. The data for close captioning is stored in the Close Caption Data register (CCDR) 38h ~ 3Bh.
Figure 3. Closed Captioning Waveform (NTSC).
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The following displays the video measurements and waveforms of the AIT2139 for NTSC(M), NTSC(EIA) and PAL(B,D,G,H,I). These measurements and waveforms were used for quantifying signal distortions and rating the performance of the AIT2139. A Tektronix VM700T Video Measurement Set, a sophisticated test and measurement instrument that digitizes the video signal and automatically analyzes it in the digital domain, were used to obtain these measurements and waveforms.
Figure 4. Color Bar (75% Amplitude, 100% Saturation) with white, yellow, cyan, green, magenta, red, blue, and black colors (from left to right) were used in the tests.
Figure 5. Vector Scope Display for NTSC Full-screen 75% Amplitude, 100% Saturation Color Bars.
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Figure 6. Horizontal Sync and Burst Interval Detail for NTSC.
Figure 7. NTSC (M) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars.
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Figure 8. NTSC (M) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars (Luminance Only).
Figure 9. NTSC (M) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars (Chrominance Only).
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Figure 10. NTSC (EIA) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars.
Figure 11. NTSC (EIA) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars (Luminance Only).
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Figure 12. NTSC (EIA) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars (Chrominance Only).
Figure 13. Vectorscope Display for PAL (B,D,G,H,I) Full-screen 75% Amplitude, 100% Saturation Color Bars.
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Figure 14. Horizontal Sync and Burst Interval Detail for PAL (B,D,G,H,I).
Figure 15. PAL (B,D,G,H,I) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars.
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Figure 16. PAL (B,D,G,H,I) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars (Luminance Only).
Figure 17. PAL (B,D,G,H,I) Composite Video Signal for 75% Amplitude, 100% Saturation Color Bars (Chrominance Only).
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Power Supply Voltages
VDDA (Measured to AGND) .................................................................................. -0.5 to +7.0V VDD (Measured to DGND) .................................................................................... -0.5 to +7.0V VDDA (Measured to VDD) ..................................................................................... -0.5 to +0.5V AGND (Measured to DGND) .................................................................................. -0.5 to +0.5V Digital Inputs Applied Voltage (Measured to DGND)2 ......................................................... -0.5 to VDD+0.5V Forced current 3, 4 ......................................................................................... -10.0 to +10.0 mA Analog Inputs Applied Voltage (Measured to AGND)2 ....................................................... -0.5 to VDDA+0.5V Forced current 3, 4 ......................................................................................... -10.0 to +10.0 mA Outputs Applied voltage (Measured to DGND)2 ....................................................... -0.5 to VDD + 0.5V Forced current 3, 4 ............................................................................................. -6.0 to +6.0 mA Short circuit duration (single output in High state to ground) ......................................... 1 second Temperature Operating, ambient .................................................................................................... 0 to 70C junction ........................................................................................................ +150C case ............................................................................................................ +140C Storage .................................................................................................................. -20 to +70C Electrostatic Discharge5 ..................................................................................................................... 150 V
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. Applied voltage must be current limited to specified range. Forcing voltage must be limited to specified range. Current is specified as conventional current flowing into the device. EIAJ test method.
2. 3. 4. 5.
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Min Nom 5.0 3.3 5.0 0 27.0000 0 31.5 50.0 18.5 18.5 2 0 50 50 0.5 0 1.25 8.92 140 50 2.0 0.8 -2.0 4.0 0 30 70 105 0.85 2.0 VRT 300 1350 53.71 85.02 Max 5.50 3.60 5.50 0.1 Units V V V V MHz Hz KHz Hz ns ns s ns ns ns V V V mA V V mA mA C C 4.00 3.00 4.00 -0.1
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Parameter VDD VDD_3.3 VDDA AGND Fxtal fXTOL fH fV tPWH tPWL tPWHS tVS-HS tS tH VRT VIN VREF IREF RREF ROUT VIH VIL IOH IOL TA Digital Power Supply Voltage SDRAM I/O Supply Voltage Analog Power Supply Voltage Analog Ground (Measured to DGND) Crystal/Reference Clock Frequency Crystal/Reference Clock Frequency Tolerance VGAHS Frequency VGAVS Frequency Reference Clock Pulse Width, High Reference Clock Pulse Width, Low VGAHS Pulsewidth VGAVS to VGAHS Delay Control Input Pulse Width, High Control Input Pulse Width, Low Reference Voltage, Top Analog Input Range External Reference Voltage D/A Converter Reference Current (IREF = VREF/RREF, flowing out of the RREF pin) Reference Resistor, VREF = Nom Total Output Load Resistance Input Voltage, Logic High Input Voltage, Logic Low Output Current, Logic High Output Current, Logic Low Ambient Temperature, Still Air
TC Case Temperature, Still Air Note: 1. For 800 X 600, 85Hz 2. Resolution for 1024 X 768 supports up to 70Hz only.
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Conditions Min Typ 300 250 200 80 35 0.988 ADCLK = Low ADCLK = High 500 1.235 3 4 12 1000 15 5 10 VDD = Max, VIN = VDD VDD = Max, VIN = 0 V -20 IOH = Max IOL = Max 2.4 0.4 10 10 -80 10 1.482 Max 400 350 270 Units mA mA mA mA mA V K pF pF K A pF pF A A mA V V CVIDEN=H, SVIDEN=H CVIDEN=L, SVIDEN=H CVIDEN=H, SVIDEN=L CVIDEN=L, SVIDEN=L VDD = Max, PWRDN = Low
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Parameter IDD IDDSV IDDCV IDDS IDDQ VRO ZRO CAI RIN ICB CI CO IIH IIL IOS VOH VOL Power Supply Current, Operating S-Video Active Composite Video Active Standby Power Supply Current, PowerDown Voltage Reference Output VREF Output Impedance Input Capacitance, A/D Input Resistance Input Current, Analog Digital Input Capacitance Digital Output Capacitance Input Current, High Input Current, Low Short-Circuit Current Output Voltage, High Output Voltage, Low
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Parameter tDS tDOV tR tF Sync Output Delay Analog Output Delay D/A Output Current Risetime D/A Output Current Falltime Conditions VGA Sync to Sync Out PXCK Out to Video Out 10% to 90% of Full Scale 90% to 10% of Full Scale 2 2 Min Typ 100 15 Max Units ns ns ns ns
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Conditions VRT = 2.0V VRT = 2.0V RT - VIN for most positive code transition VIN for most negative code transition -20 30 Min Typ 0.3 0.3 30 45 65 80 110 Max 0.5 0.5 Units LSB LSB ps mV mV
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Parameter ELI ELD EAP EOT EOB A/D Integral Linearity Error, Independent A/D Differential Linearity Error Aperture Error Offset Voltage, Top Offset Voltage, Bottom
Note: Values shown in Typ column are typical for VDD = VDDA = +5V and TA = 25C.
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Parameter RES dp dg CNLP CNLG PSRR D/A Converter Resolution Differential Phase Differential Gain Chroma Nonlinear Phase Chroma Nonlinear Gain Power Supply Rejection Ratio PXCK = 27 MHz, 40 IRE Ramp PXCK = 27 MHz, 40 IRE Ramp NTC-7 Combination NTC-7 Combination CBYP = 0.1 F, f = 1 KHz 0.5 Conditions Min 10 Typ 10 0.5 1.5 1.25 1.0 Max 10 Units Bits degree % degree % %/ %VDD
Notes: 1. Noise Level is unified weighted, 10 kHz to 5.0 MHz bandwidth, with Tilt Null ON measured using VM700 "Measure Mode." 2. Noise Level is unified weighted, 10 kHz to 5.0 MHz bandwidth, measured using VM700 "Auto Mode".
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Table 18. AIT2139 MQFP Package - Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name VDD DGND RESET\ NC T_EN VDD DGND NC VDD GNDPLL PLL_LPF VDDPLL * VDD_3.3 MW_CLK MW_RST MW_EN PDO_0 PDO_1 DGND PDO_2 PDO_3 PDO_4 PDO_5 PDO_6 PDO_7 PDO_8 PDO_9 PDO_10 DGND NC PDO_12 PDO_13 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name PDO_14 PDO_15 NC * VDD_3.3 PDI_0 PDI_1 PDI_2 PDI_3 PDI_4 DGND PDI_5 PDI_6 PDI_7 PDI_8 PDI_9 PDI_10 PDI_11 PDI_12 PDI_13 DGND PDI_14 PDI_15 NC NC NC * VDD_3.3 VDD NC XTAL1 XTAL2 DGND AGND Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name VDDA SVIDEN CVIDEN NC C_COMP RREF VDD LUMA PWRDN VREF COMP
AGND
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Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name DGND TVSTD0 NC
VDD
CHROMA VDDA VDDA VTIN VTOUT CSYNC
R
AGND VDDA EN_RST\ DGND G AGND TVSTD1 VDDA
VDD
VRT B AGND VDDA
VDD ZOOM PAL_NTSC FILTER OVRSCN YUV_OUT RGB_OUT AGND VDD POSD POSR POSL POSU DGND VDD I2C_SCL I2C_ADR I2C_SDA DGND PHASE SDR BLANK FREEZE DGND HSRAW HSOUT VSRAW VSOUT
Note: NC should be open, not connected to ground or VCC. * This Pin also can be connected to VDD.
Figure 19. 128 Lead Metric Quad Flat Pack (MQFP) Outline
102 65
103
64
128
39
1
38
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Figure 20. AIT2139 128-Lead Metric Quad Flat Pack (MQFP) Dimensions NOTE: 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. BUT MOLD MISMATCH IS INCLUDED. ALLOWABLE PROTRUSION IS .25MM PER SIDE. 2. DIMENTION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION .08MM TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 3. CONTROLLING DIMENSION: MILLIMETER.
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A A
1
Min
Dimension ( mm) Nom Max
--0.25 2.73 0.17 0.09 23.00 19.90 17.00 13.90
----2.85 0.22 --23.20 20.00 17.20 14.00 0.5 BSC
3.40 --2.97 0.27 0.20 23.40 20.10 17.40 14.10
A
2
B C D D
1
E E
1
e L L
1
0.73
0.88 1.60 BSC
1.03
Y
--0
-----
0.10 7
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D D1
102 65
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128
39
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The Twist Company 3433 Broadway St. N.E. Minneapolis, MN 55413 TEL: (612) 331-1212 FAX: (612) 331-8783 Genesis Marketing 224 Church St. NW Suite 1 Huntsville, AL 35801 TEL: (205) 534-3097 FAX: (205) 534-1034 Genesis Marketing 7001 Peachtree Industrial Blvd. #205, Nacross, GA 30092 TEL: (770) 840-7560 FAX: (770) 840-9651 WD Sales, Inc. 42 Water Street Eastchester, NY 10709 TEL: (914) 779-8738 FAX: (914) 779-8840 WD Sales, Inc. 52 Warren Way Burlington Township, NJ 08016 TEL: (609) 386-9014 FAX: (609) 386-7037
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China Office: AITech Shanghai Co., Ltd. 18 Cao Xi Bei Road, 21FL Suite F Shanghai 200030, People's Republic of China TEL: (86) 21-6427-1899 FAX: (86) 21-6427-1900 Taiwan Office: AITech-Taiwan 9F, No2, Alley6, Lane 235, Pao Chiao Rd. Hsintien, Taiwan, R.O.C. TEL: (886) 2-2915-7569 FAX: (886) 2-2915-6278 Japan Distributor: Nichimen Electronic Components Corp. HokoOku Bldg., 9F, 6-28 Nakatsu 1-Chome, Kita-Ku Osaka, 531 Japan TEL: (81) 6-375-7720 FAX: (81) 6-375-7730 Taiwan Distributor: Silicon Application Corp. 7F, No. 14 Lane 235, Pao Chia Rd. Hsin Tien, Taipei Hsien, Taiwan TEL: (886) 2-2917-8855 FAX: (886) 2-2917-1622 Holy Stone Enterprise, Co. Ltd. 1 Fl., No. 62, Sec. 2, Huang Shan Rd. Neu Hu Dist., Taipei, Taiwan TEL: (886) 2-2627-0383 FAX: (886) 2-2798-7181 Synnex Technology International Corp. 4th Fl., 75, Sec. 3, Ming-Sheng E. Rd. Taipei, Taiwan, R.O.C. TEL: (886) 2-2506-3320 FAX: (886) 2-2504-8081 Singapore Rep.: INSTEP MicroSolutions Pte., Ltd. 18, Tannery Lane, #05-02 Lian Tong Building, Singapore 347780 TEL: (65) 741-7507 FAX: (65) 741-1478 Korea Rep.: Global Exchange Trading Co. #301 Samgin Bldg, 165-2 Poi-Dong Kangnam-Ku, Seoul Korea 135-26 TEL: (82)-2-3462-0333 FAX: (82)-2-3462-0549 United Kingdom: K9 Technology Ltd. Upper Level, The Dutch Barn Elm Tree Park, Manto, Marlborough SN81PS, UK TEL: (44) 1672-861000 FAX: (44) 1672-861010 North America: Quorum Technical Sales 4701 Patrick Henry Drive Bldg. 12, Santa Clara, CA 95054 TEL: (408) 980-0812 FAX: (408) 748-1163
AITech International Corp.
World Headquarters 47987 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 226-8960 * (800) 882-8184 * Fax: (510) 226-8996 http://www.aitech.com * E-mail: icsales@aitech.com
(c)1998-1999 AITech International Corporation. All Rights Reserved. Specifications subject to change without notice. AITech, VSPro, and Flic-Free are trademarks of AITech International Corporation AITech PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF AITech. Information furnished by AITech International Corporation is believed to be accurate and reliable. However, no responsibility is assumed by AITech International Corporation for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of AITech International Corporation.
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